Is possible to get the state information from L1 cache line protocol in a different core?

There are several cache coherence protocols around there, such as MSI, MESI, MOSI, MOESI, etc.

Let's suppose this scenario: A CPU contains 4-cores with L1 private cache (L1 cache size does not matter here). The memory addresses here are illustrative.

  1. Core-0 requests a memory access to address 0x1111, thus the value will be loaded into its L1 cache line from the main memory.

  2. Core-1 requests a memory access to address 0x2222, thus the value will be loaded into its L1 cache line from the main memory.

  3. Core-2 requests a memory access to address 0x1111 (previously accessed by Core-0). This reference is already loaded into Core-0's cache line, thus, the cache coherence protocol will copy the Core-0's cache line that contains the reference and finally store it into Core-2's cache line.

Question 1: Does core-2 knows that the memory access has been served by Core-0's cache line instead of main memory? Or the Cache Coherence Protocol is transparent to where the data has been retrieved?

Question 2: Core-0, and Core-2 have their cache line in Shared state after step 3. However, is possible to Core-2 gets the currently state from a given memory reference from a different core? In this case, is possible Core-2 knows that for this memory reference 0x1111 Core-0 cache line is in Shared state?

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